1. Field of the Invention
The present invention relates to a method of a burn-in test, which is one of screening methods (potential defect screening methods) for semiconductor integrated circuits.
2. Description of the Background Art
FIG. 10 is a characteristic diagram illustrating a failure rate curve (bathtub curve) showing the relation between elapsed times in actual working states and failure rates as to semiconductor integrated circuits or the like.
In an initial failure period A, failures are caused by defects in manufacturing, i.e., potential defects to be removed by screening. In a chance failure period B, failures are caused by chance in normal products after screening of the potential defects, and the failure rate is stably minimized in this period. In a wear-out failure period C, normal products are wasted and deteriorated with time to increase the failure rate.
A burn-in test is performed in order to remove products having potential defects which are caused during manufacturing steps corresponding to the initial failure period A thereby ensuring reliability of shipped products. FIG. 11 illustrates a state of such a burn-in test.
A semiconductor integrated circuit 1 which is completely assembled is set on a socket 2, and arranged in the interior of a thermostat 3 as a whole to be connected to a voltage application device 4. The voltage application device 4 applies a source voltage which is higher than that in actual working conditions to the semiconductor integrated circuit 1, while the thermostat 3 supplies an atmosphere temperature which is higher than that in the actual working conditions for performing aging. The burn-in test is made under severer conditions than the actual working conditions, in order to detect and screen initial hilures in a short time by accelerating aging. However, the thermostat 3 may supply an atmosphere temperature which is lower than that in the actual working conditions for performing aging, as the case may be.
As hereinabove described, the burn-in test, which is a screening method for a semiconductor integrated circuit, has been generally carried out on a finished product after packaging.
However, it has been recognized that potential defects related to initial failures are not caused in an assembling step but mostly caused in a wafer process. For example, a defect in an insulating film of a MIS (metal insulator semiconductor) integrated circuit represented by a VLSI (very large scale integrated circuit) is caused in the wafer process.
However, the conventional burn-in test is carried out on the semiconductor integrated circuit 1 being passed through the assembling step, as hereinabove described. Even if a potential defective chip already has a defect in a wafer process, therefore, the defect cannot be found through the burn-in test until the next assembling step is completed.
If the defect is not found until the burn-in test is carried out after the assembling step, the assembling step following the wafer process itself results in vain to deteriorate the throughput. Further, various materials employed for the assembling step are so wasted that the situation is extremely unadvantageous in cost as a whole.
Further, failure analysis and feedback to the wafer process, i.e., countermeasures such as discovery of abnormality in the process line and maintenance are inevitably retarded to cause reduction in yield. This also exerts such an unpreferable influence that the speed of development of new products is retarded.
On the other hand, a wafer test (functional test) of performing energization in a wafer state is generally known as a test which is not a burn-in test but made after completion of a wafer process. FIG. 12 is a perspective view showing a state of such a wafer test, and FIG. 13 is aside elevational view thereof.
A chip 5b having a plurality of bonding pads is formed on a major surface 5a of a semiconductor wafer 5. Metal probers 6 are brought into contact with respective ones of these bonding pads. The "bonding pads" are connection regions of bonding wires for connecting circuit elements provided on a semiconductor wafer with external electrode terminals in an assembling step, as is well known in the art.
The wafer test is carried out by applying a voltage or a current through a certain metal prober 6 and extracting the voltage or current by another metal prober 6.
The respective ones of the plurality of metal probers 6 are brought into contact with the bonding pads of the chip 5b in inclined states. In this case, contact pressures of the metal probers 6 for the bonding pads can be easily uniformalized.
When the metal probers 6 arc thus inclined, however, only one chip 5b can be tested in a single wafer test and it is impossible to simultaneously test a plurality of such chips 5b. In the case of a burn-in test, an extremely long time is required if tens of chips 5b provided on a single wafer 5 are entirely tested one by one, since energization for tens of hours is required for testing one chip 5b. Thus, it is impractical to carry out a burn-in test while inclining the metal probers 6.
Then, consider that the metal probers 6 are brought into contact with the bonding pads perpendicularly to the major surface 5a as shown in FIG. 14. In this case, it may be possible to simultaneously apply voltages to all chips 5b.
In recent years, however, a semiconductor integrated circuit such as a microprocessor or a gate array is so increasingly improved in scale that a single chip is provided with 100 or more bonding pads. Thus, it is physically impossible to accurately bring the metal probers 6 into contact with all bonding pads of all chips 5b provided on the semiconductor wafer 5 in perpendicular states with constant pressures.
When the metal probers 6 arc employed for carrying out screening in a wafer state similarly to the wafer test, therefore, an extremely long time is required as hereinabove described.